| Author | Title | Publication Name | Year |
|---|
| Minsoo Kim | PROBE3.0: A Systematic Framework for
Design-Technology Pathfinding with Improved
Design Enablement | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (submitted) | 2023 |
| Alexander Graening, Saptadeep Pal, Puneet Gupta | Chiplets: How Small is too Small? | Design Automation Conference | 2023 |
| C. Chidambaram, A. B. Kahng, M. Kim, G. Nallapati, S.C. Song and M. Woo | A Novel Framework for DTCO: Fast and Automatic Routability Assessment with Machine Learning for Sub-3nm Technology Options | Proc. IEEE Symposium on VLSI Technology | 2021 |
| Andrew R. Neureuther, Luke Long, and Patrick Naulleau | Modeling stochastic effects of exposure/diffusion and dissolution on missing contacts | SPIE Proc. 11609 Extreme Ultraviolet (EUV) Lithography XII | 2021 |
| S. Pal and P. Gupta | Pathfinding for 2.5D Interconnect Technologies | System-Level Interconnect – Problems and Pathfinding Workshop | 2020 |
| Jonathan H. Ma, Han Wang, David Prendergast, Andrew Neureuther, Patrick Naulleau | Excitation selectivity in model tin-oxo resist: a computational chemistry perspective | Proceedings Volume 11323, Extreme Ultraviolet (EUV) Lithography XI | 2020 |
| Luke Long, Andrew Neureuther, Patrick Naulleau | Measurement of latent image in resist using scanning probe techniques | Proc. SPIE. 11323, Extreme Ultraviolet (EUV) Lithography XI | 2020 |
| S. Jangam, U. Rathore, S. Nagi, D. Markovic, and S. S. Iyer | Demonstration of a Low Latency (<20 ps) Fine-pitch (≤10 µm) Assembly on the Silicon Interconnect Fabric | IEEE 70th Electronic Components and Technology Conference (ECTC) | 2020 |
| R. Irwin, Y. Hu, A. Alam, S. Benedict, T. Fisher, S. S. Iyer | Nanowire Impregnated Poly-dimethyl Siloxane for Flexible, Thermally Conductive Fan-Out Wafer-level Packaging | IEEE 70th Electronic Components and Technology Conference (ECTC) | 2020 |
| S. Pal, D. Petrisko, R. Kumar and P. Gupta | Design Space Exploration for Chiplet-Assembly-Based Processors | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2020 |
| C.-K Cheng, A. B. Kahng, H. Kim, M. Kim, D. Lee, D. Park and M. Woo | PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes | IEEE Trans. on CAD (In Submission) | 2020 |
| Xia Sang, Jane P Chang | Patterning nickel for extreme ultraviolet lithography mask application. II. Hybrid reactive ion etch and atomic layer etch processing | Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films | 2020 |
| Xia Sang, Ernest Chen, Jane P Chang | Patterning nickel for extreme ultraviolet lithography mask application I. Atomic layer etch processing | Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films | 2020 |
| Xia Sang, Yantao Xia, Philippe Sautet, Jane P Chang | Atomic layer etching of metals with anisotropy, specificity, and selectivity | Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films | 2020 |
| Xia Sang, Jane P Chang | Physical and chemical effects in directional atomic layer etching | Journal of Physics D: Applied Physics | 2020 |
| Woojin Choi, Renjie Chen, Cooper Levy, Atsunori Tanaka, Ren Liu, Venkatesh Balasubramanian, Peter M. Asbeck, and Shadi A. Dayeh, , available online, 2020 | Intrinsically linear transistor for millimeter-wave low noise amplifiers | Nano Letters | 2020 |
| Jonathan H. Ma, Han Wang, David Prendergast, Andrew Neureuther, Patrick Naulleau | Investigating EUV radiation chemistry with first principle quantum chemistry calculations | Proceedings Volume 11147, International Conference on Extreme Ultraviolet Lithography 2019; | 2019 |
| Jonathan Ma, Andrew R. Neureuther, Patrick P. Naulleau | Investigating EUV radiochemistry with condensed phase photoemission | Proceedings Volume 10957, Extreme Ultraviolet (EUV) Lithography X; 109571Y (2019) | 2019 |
| Luke Long, Andrew Neureuther, Patrick Naulleau | Modeling of novel resist technologies | Proc. SPIE. 10960, Advances in Patterning Materials and Processes XXXVI | 2019 |
| A. Alam, A. Hanna, R. Irwin, G. Ezhilarasu, H. Boo, Y. Hu, C. W. Wong, T. S. Fisher, and S. S. Iyer | Heterogeneously Integrated Foldable Display on Elastomeric Substrate Based on Fan-Out Wafer Level Packaging | IEEE 69th Electronic Components and Technology Conference (ECTC) | 2019 |
| Eugene Chu, Yandong Luo, and Puneet Gupta | Design Impacts of Back-End-Of-Line Line Edge Roughness | IEEE Transactions on Semiconductor Manufacturing | 2019 |
| S. Jangam et al. | Fine-Pitch (≤10 µm) Direct Cu-Cu Interconnects Using In-Situ Formic Acid Vapor Treatment | 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) | 2019 |
| Stuart Sherwin | Advanced multilayer mirror design to mitigate EUV shadowing | Proceedings of SPIE Advanced Lithography | 2019 |
| C.-T. Ho and A. B. Kahng | IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop | Proc. ACM/IEEE International Conference on Computer-Aided Design | 2019 |
| A. B. Kahng, H.-Y. Liu, C. Park, R. Pichumani, and L. Saul | SVM Learning for GFIS Trimer Health Monitoring in Helium-Neon Ion Beam Microscopy | Proc. Advanced Process Control Conference | 2019 |
| Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar | Architecting Waferscale Processors - A GPU Case Study | International Symposium on High Performance Computer Architecture (HPCA) | 2019 |
| Uday Mallappa, Lawrence Saul, Shangyuan Tong, Andrew B. Kahng | "Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design | 2019 Design, Automation & Test in Europe Conference & Exhibition | 2019 |
| Seokhyeong Kang, Seungwon Kim, Kambiz Samadi, Bangqi Xu, Andrew B. Kahng | Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology | 2019 Design, Automation & Test in Europe Conference & Exhibition | 2019 |
| Sun ik Heo, Minsoo Kim, Lutong Wang, Chutong Yang, Andrew B. Kahng | Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI | 2019 Design, Automation & Test in Europe Conference & Exhibition | 2019 |
| Sun ik Heo, Andrew. B. Kahng, Minsoo Kim, Lutong Wang and Chutong Yang | Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI | Design, Automation and Test in Europe | 2019 |
| Sun ik Heo, Andrew. B. Kahng, Minsoo Kim and Lutong Wang | Diffusion Break-Aware Leakage Power Optimization and Detailed Placement in Sub-10nm VLSI | Asia and South Pacific Design Automation Conference | 2019 |
| Luke Long, Andrew Neureuther, Patrick Naulleau | Measurement and modeling of diffusion characteristics in EUV resist | Proc. SPIE. 10809, International Conference on Extreme Ultraviolet Lithography 2018 | 2018 |
| Xuefeng Gu, S. S. Iyer | Unsupervised Learning Using Charge-Trap Transistors | IEEE Electron Device Letters | 2018 |
| Gautam Gunjala, Stuart Sherwin, Aamod Shanker | Field-varying aberration recovery in EUV microscopy using mask roughness | Computational Optical Sensing and Imaging | 2018 |
| Stuart Sherwin | EUV mask characterization with actinic scatterometry | Proceedings of SPIE Photomask Technology + Extreme Ultraviolet Lithography | 2018 |
| Gautam Gunjala, Stuart Sherwin, Aamod Shanker | Aberration recovery by imaging a weak diffuser | Optics express | 2018 |
| Yoo-Jin Chae, Rik Jonckheere, Puneet Guptaa | Defect Avoidance for Extreme Ultraviolet Mask Defects using Intentional Pattern Deformation | International Conference on Extreme Ultraviolet Lithography | 2018 |
| Y. Luo and P. Gupta | Relaxing ler requirement in euv lithography | SPIE Advanced Lithography | 2018 |
| W.-C. Wang, C. Zhao, and P. Gupta | Assessing Layout Density Benefits of Vertical Channel Devices | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2018 |
| Saptadeep Pal, Daniel Petrisko, Adeel A. Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar | A Case for Packageless Processors | IEEE International Symposium on High Performance Computer Architecture (HPCA) | 2018 |
| A. A. Bajwa, S. Jangam, S. Pal, B. Vaisband, R. Irwin, M. Goorsky, and S. S. Iyer | Demonstration of a h eterogeneously integrated System-on-Wafer (SoW) assembly | Electronic Components and Packaging Technology (ECTC) | 2018 |
| S. Jangam, A. Bajwa, K. K. Thankappan, P. Kittur and S. S. Iyer | Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric | Electronic Components and Packaging Technology (ECTC) | 2018 |
| Stuart Sherwin | Actinic EUV Scatterometry for Parametric Mask
Quantification | Proceedings of SPIE-Advanced Lithography | 2018 |
| Hongseok Oh, JunBeom Park, Woojin Choi, Heehun Kim, Youngbin Tchoe, Arpana Agrawal, Gyu‐Chul Yi | Vertical ZnO Nanotube Transistor on a Graphene Film for Flexible Inorganic Electronics | Small | 2018 |
| Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta | Advanced Packaging and Heterogeneous Integration to Reboot Computing | IEEE International Conference on Rebooting Computing (ICRC) | 2017 |
| A. B. Kahng, H. Lee and J. Li | PROBE: Placement, Routing, Back-End-of-Line Measurement Utility | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2017 |
| A. A. Bajwa, S. Jangam, S. Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, and S. S. Iyer | Heterogeneous Integration at Fine Pitch (≤ 10 μm) using Thermal Compression Bonding | Electronic Components and Packaging Technology (ECTC) | 2017 |
| S. Jangam, S. Pal, A. Bajwa, S. Parmarti, P. Gupta and S. S. Iyer | Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme | Electronic Components and Packaging Technology (ECTC) | 2017 |
| Stuart Sherwin | Modeling high-efficiency extreme
ultraviolet etched multilayer phase-shift
masks | Journal of Micro/Nanolithography, MEMS, and MOEMS | 2017 |
| Rui La, Ren Liu, Weichuan Yao, Renjie Chen, Mattias Jansson, Janet L Pan, Irina A Buyanova, Jie Xiang, Shadi A Dayeh, Charles W Tu | Self-catalyzed core-shell GaAs/GaNAs nanowires grown on patterned Si (111) by gas-source molecular beam epitaxy | Applied Physics Letters | 2017 |
| Shadi A Dayeh, Renjie Chen, Yun Goo Ro, Joonseop Sim | (Invited) Issues for the Doping of Semiconductor Nanowires During Growth | Materials Science in Semiconductor Processing | 2017 |
| Ren Liu, Renjie Chen, Ahmed T Elthakeb, Sang Heon Lee, Sandy Hinckley, Massoud L Khraiche, John Scott, Deborah Pre, Yoontae Hwang, Atsunori Tanaka, Yun Goo Ro, Albert K Matsushita, Xing Dai, Cesare So | High Density Individually Addressable Nanowire Arrays Record Intracellular Activity from Primary Rodent and Human Stem Cell Derived Neurons | Nano Letters | 2017 |
| Atsunori Tanaka, Woojin Choi, Renjie Chen, Shadi A Dayeh | Si Complies with GaN to Overcome Thermal Mismatches for the Heteroepitaxy of Thick GaN on Si | Advanced Materials | 2017 |
| Renjie Chen, Xing Dai, Katherine L Jungjohann, William Moyer Mook, John Nogan, Cesare Soci, Shadi A. Dayeh | (Invited) The Dynamics of Nickelidation for Self-Aligned Contacts to InGaAs Channels | ECS Transactions | 2017 |
| Renjie Chen, Binh-Minh Nguyen, Wei Tang, Yang Liu, Jinkyoung Yoo, Shadi A Dayeh | “In-situ Control of Synchronous Germanide/Silicide Reactions with Ge/Si Core/Shell Nanowires to Monitor Formation and Strain Evolution in Abrupt 2.7nm Channel Length | Applied Physics Letters | 2017 |
| Renjie Chen, Shadi A Dayeh | Recordings and Analysis of Atomic Ledge and Dislocation Movements in InGaAs to Nickelide Nanowire Phase Transformation | Small | 2017 |
| Renjie Chen, Katherine L Jungjohann, William M Mook, John Nogan, Shadi A Dayeh | Atomic Scale Dynamics of Contact Formation in the Cross-section of InGaAs Nanowire Channels | Nano Letters | 2017 |
| Nicholas D. Altieri, Jack Kun-Chieh Chen, Luke Minardi, and Jane P. Chang | Plasma-surface interactions at the atomic scale for patterning metals | Journal of Vacuum Science & Technology A | 2017 |
| Jack Kun-Chieh Chen, Nicholas D. Altieri, Taeseung Kim, Ernest Chen, Thorsten Lill, Meihua Shen, and Jane P. Chang | Directional etch of magnetic and noble metals. II. Organic chemical vapor etch | Journal of Vacuum Science & Technology A | 2017 |
| Jack Kun-Chieh Chen, Nicholas D. Altieri, Taeseung Kim, Thorsten Lill, Meihua Shen, and Jane P. Chang | Directional etch of magnetic and noble metals. I. Role of surface oxidation states | Journal of Vacuum Science & Technology A | 2017 |
| Jack Kun-Chieh Chen, Taeseung Kim, Nicholas D. Altieri, Ernest Chen, and Jane P. Chang | Ion beam assisted organic chemical vapor etch of magnetic thin films | Journal of Vacuum Science & Technology A | 2017 |
| Suchit Bhattarai, Andrew R. Neureuther, Patrick P. Naulleau | Contrast Curves for Low Energy Electron Exposures of an EUV
Resist in a Scanning Electron Microscope | SPIE Advanced Lithography Conference | 2017 |
| Yasmine Badr, Puneet Gupta | Technology path-finding framework for directed-self assembly for via layers | Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3) | 2017 |
| Yasmine Badr, Puneet Gupta | Technology Path-finding for Directed Self-Assembly for Via Layers | SPIE Advanced Lithography | 2017 |
| P. Debacker, K. Han, A. B. Kahng, H. Lee, P. Raghavan and L. Wang | MILP-Based Optimization of 2D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2017 |
| W.-T. J. Chan, A. B. Kahng and J. Li | Revisiting 3DIC Benefit with Multiple Tiers | Integration: The VLSI Journal | 2017 |
| T.-B. Chan, P. Gupta, K. Han, A. A. Kagalwalla and A. B. Kahng | Benchmarking of Mask Fracturing Heuristics | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2017 |
| K. Han, A. B. Kahng, H. Lee and L. Wang | Performance- and Energy-Aware Optimization of BEOL Interconnect Stack Geometry in Advanced Technology Nodes | IEEE Intl. Symp. on Quality in Electronic Design | 2017 |
| W.-T. J. Chan, P.-H. Ho, A. B. Kahng and P. Saxena | Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning | ACM/IEEE Intl. Symp. on Physical Design | 2017 |
| Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan and Lutong Wang | Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes | ACM/IEEE Design Automation Conf. | 2017 |
| Yow-Gwo Wang, Andy Neureuther, Patrick Naulleau | Impact of tool design on defect detection sensitivity for EUV actinic blank inspection | SPIE Advanced Lithography | 2017 |
| YG Wang, S Hsu, R Socha, A Neureuther, P Naulleau | Impact of EUV SRAF on Bossung tilt | SPIE Advanced Lithography | 2017 |
| AamodShanker, Antoine Wojdyla, Markus Benk, Patrick Naulleau, Laura Waller | Characterizing EUV aerial imaging tool aberrations using photomask substrate roughness | SPIE Advanced Lithography | 2017 |
| Aamod Shanker | Characterizing EUV aerial imaging tool aberrations using photomask substrate roughness | SPIE Advanced Lithography | 2017 |
| Stuart Sherwin | Rigorous 3D electromagnetic simulation of ultrahigh efficiency EUV contact-hole printing with chromeless phase shift mask | SPIE Advanced Lithography | 2017 |
| A. B. Kahng, H. Lee and J. Li | Measuring Progress and Value of IC Implementation Technology | IEEE/ACM International Conference on Computer-Aided Design | 2016 |
| W.-T. J. Chan, Y. Du, A. B. Kahng, S. Nath and K. Samadi | BEOL Stack-Aware Routability Prediction from Placement Using Data Mining Techniques | IEEE Intl. Conf. on Computer Design | 2016 |
| Yow-Gwo Wang; Andrew Neureuther; Patrick Naulleau | Impact of noise sources and optical design on defect sensitivity for EUV actinic pattern inspection | SPIE Advanced Lithography | 2016 |
| Yow-Gwo Wang; Andrew Neureuther; Patrick Naulleau | Enhancing native defect sensitivity for EUV actinic blank inspection: optimized pupil engineering and photon noise study | SPIE Advanced Lithography | 2016 |
| S. Bang, K. Han, A. B. Kahng and M. Luo | Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products | Asia and South Pacific Design Automation Conf. | 2016 |
| A. B. Kahng, J. Li and L. Wang | Improved Flop Tray-Based Design Implementation for Power Reduction | IEEE/ACM International Conference on Computer-Aided Design | 2016 |
| K. Y. Chung, A. B. Kahng and J. Li | Comprehensive Optimization of Scan Chain Timing During Late-Stage IC Implementation | ACM/IEEE Design Automation Conf. | 2016 |
| W.-T. J. Chan, A. B. Kahng and J. Li | Revisiting 3DIC Benefit with Multiple Tiers | ACM/IEEE International Workshop on System-Level Interconnect Prediction | 2016 |
| K. Han, A. B. Kahng and J. Li | Improved Performance of 3DIC Implementations Through Inherent Awareness of Mix-and-Match Die Stacking | Design, Automation and Test in Europe | 2016 |
| Aamod Shanker | Feature size dependence of mask topography induced phase effects in an aerial imaging tool | SPIE Photomask | 2016 |
| Yasmine Badr, Puneet Gupta | Technology path-finding for directed self-assembly for via layers | SPIE Advanced Lithography | 2016 |
| Yasmine Badr, Andres Torres, Puneet Gupta | Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for sub-7nm Contact/Via Holes | IEEE Transactions on CAD | 2016 |
| Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian Iyer, and Puneet Gupta | Assessing Benefits of a Buried Interconnect Layer in Digital Designs | IEEE Transactions on CAD | 2016 |
| Suchit Bhattarai, Andrew R. Neureuther, Patrick P. Naulleau | Study of Energy Delivery and Mean Free Path of Low Energy Electrons in EUV Resists | Proceedings of SPIE | 2016 |
| Wei-Che Wang and Puneet Gupta | Efficient Layout Generation and Design Evaluation
of Vertical Channel Devices | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) | 2016 |
| A. B. Kahng, S. Kang, J. Li, and J. Pineda de Gyvez | An Improved Methodology for Resilient Design Implementation | ACM Transactions on Design Automation of Electronic Systems | 2015 |
| Peng Zheng, Daniel Connelly, Fei Ding and Tsu-Jae King Liu | Simulation-Based Study of the Inserted-Oxide FinFET for Future Low-Power System-on-Chip Applications | Electron Device Letters, IEEE | 2015 |
| Yow-Gwo Wang, Andy Neureuther, Patrick Naulleau | The study of phase effects in EUV mask pattern defects | 2015 SPIE Photomask Technology | 2015 |
| Yow-Gwo Wang, Ryan Miyakawa, Weilun Chao, Markus Benk, Antoine Wojdyla, Alex Donoghue, David Johnson, Kenneth Goldberg, Andy Neureuther, Ted Liang, Patrick Naulleau | Enhancing defect detection with Zernike phase contrast in EUV multilayer blank inspection | SPIE Advanced Lithogrpahy | 2015 |
| Suchit Bhattarai, Weilun Chao, Shaul Aloni, Andrew R. Neureuther, Patrick P. Naulleau | Analysis of Shot Noise Limitations due to Absorption Count in EUV Resists | SPIE Advanced Lithography | 2015 |
| R. A. Claus, Y.-G.Wang, A. Wojdyla, M. P. Benk, K. A. Goldberg, A. R. Neureuther, P. P. Naulleau, L. Waller | Phase measurements of EUV mask defects | SPIE Advanced Lithography | 2015 |
| R. A. Claus, A. Wojdyla, M. P. Benk, K. A. Goldberg, A. R. Neureuther, P. P. Naulleau, L. Waller | Aberration estimation using EUV mask roughness | SPIE Advanced Lithography | 2015 |
| Aamod Shanker, Lei Tian, Martin Sczyrba, Falk Lange, Brid Connolly, Andy Neureuther, and L. Waller | Characterizing the dependence of thick-mask edge effects on feature size and illumination angle using AIMS images | SPIE Advanced Lithography | 2015 |
| Kwangsoo Han, Andrew B, Kahng, jongpil Lee, Jiajia Li and Siddhartha Nath | A Global-Local Optimization Framework for Simultaneous Multi-Mode Multi-Corner Clock Skew Variation Reduction | DAC | 2015 |
| Taeseung Kim, Younghee Kim, Jack Kun-Chieh Chen, and Jane P. Chang | Viable chemical approach for patterning nanoscale magnetoresistive random access
memory
magnetic metal elements | Journal of Vacuum Science & Technology A | 2015 |
| Kwangsoo Han, Andrew B. Kahng and Hyein Lee, | Evaluation of BEOL Design Rule Impacts Using an Optimal ILP-Based Detailed Router | Design Automation Conference (DAC) | 2015 |
| Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta | CEED: A Pareto Optimization-based Circuit-level Evaluator for Emerging Devices | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | 2015 |
| Abde Ali Kagalwalla, Puneet Gupta | Effective Model-Based Mask Fracturing for Mask Cost
Reduction | Design Automation Conference (DAC) | 2015 |
| Yasmine Badr, Andres Torres, Puneet Gupta | Incorporating DSA in multipatterning semiconductor
manufacturing technologies | SPIE | 2015 |
| Yasmine Badr, Andres Torres, Puneet Gupta | Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias | Design Automation Conference (DAC) | 2015 |
| Yasmine Badr, Andres Torres, Puneet Gupta | Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts/Vias | Design Automation Conference (DAC) | 2015 |
| Peng Zheng, Yi-Bo Liao, Nattapol Damrongplasit, Meng-Hsueh Chiang and Tsu-Jae King Liu | Variation-Aware Comparative Study of 10-nm GAA
Versus FinFET 6-T SRAM Performance and Yield | IEEE TRANSACTIONS ON ELECTRON DEVICES | 2014 |
| Rene A. Claus, Andrew R. Neureuther, Patrick P. Naulleau, Laura Waller | Effect of Amplitude Roughness on EUV Mask Specification | SPIE Photomask Technology 2014 | 2014 |
| Aamod Shanker, Lei Tian, Martin Sczyrba, Brid Connolly, Andy Neureuther, Laura Waller | Transport of Intensity phase imaging in the presence of curl effects induced by strongly absorbing photomasks | Applied Optics | 2014 |
| Taeseung Kim, Jack Kun-Chieh Chen, and Jane P. Chang | Thermodynamic assessment and experimental verification of reactive ion etching of
magnetic metal elements | Journal of Vacuum Science & Technology A | 2014 |
| Yasmine Badr, Ko-wei Ma, Puneet Gupta | Layout Pattern-driven Design Rule Evaluation | JM3 | 2014 |
| Yow-Gwo Wang, Ryan Miyakawa, Weilun Chao, Kenneth Goldberg, Andy Neureuther, and Patrick Naulleau | Phase-enhanced defect sensitivity for EUV mask inspection | SPIE Photomask Technology 2014 | 2014 |
| Wei-Che Wang and Puneet Gupta | Efficient Layout Generation and Evaluation of Vertical Channel Devices | International Conference on Computer-Aided Design (ICCAD) | 2014 |
| Aamod Shanker, Martin Sczyrba, Brid Connolly, Franklin Kalk, Andy Neureuther, Laura Waller | Critical Assessment of the Transport of Intensity Equation as
a phase recovery technique in optical lithography | SPIE Advanced Lithography | 2014 |
| Suchit Bhattaraia, Weilun Chao, Andrew R. Neureuther, Patrick P. Naulleau | Comparative Analysis of Shot Noise in EUV and E-Beam Lithography | Proceedings of SPIE | 2014 |
| Tuck Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng and Emile Sahouria | Benchmarking of Mask Fracturing Heuristics | International Conference on Computer-Aided Design (ICCAD) | 2014 |
| Rene A. Claus; A. R. Neureuther; L. Waller; P. P. Naulleau | Predicting LER PSD Caused by Mask Roughness Using a Mathematical Mode | SPIE Advanced Lithography 2014 | 2014 |
| Yow-Gwo Wang, Ryan Miyakawa, Andy Neureuther, Patrick Naulleau | Zernike phase contrast microscope for EUV mask inspection | SPIE Advanced Lithography | 2014 |
| Abde Ali Kagalwalla and Puneet Gupta | Comprehensive Defect Avoidance Framework for Mitigating EUV Mask Defects | SPIE Advanced Lithography Symposium | 2014 |
| A. A. Kagalwalla, M. Lam, K. Adam, and P. Gupta | EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts | Proc. Asia and South Pacific Design Automation Conference | 2014 |
| Rene A. Claus ; I. Mochi ; M. P. Benk ; K. A. Goldberg ; A. R. Neureuther ; P. P. Naulleau | Recovering effective amplitude and phase roughness of EUV masks | Photomask Technology 2013 | 2013 |
| Abde Ali Kagalwalla and Puneet Gupta | Design-Aware Defect-Avoidance Floorplanning of EUV Masks | IEEE Transactions on Semiconductor Manufacturing | 2013 |
| Rani S. Ghaida, Mukul Gupta and Puneet Gupta | A Framework for Exploring the Interaction between Design Rules and Overlay Control | SPIE Advanced Lithography 2013 | 2013 |
| Rene A. Claus, Andrew R. Neureuther, Patrick P. Naulleau | Mathematical model for calculating speckle contrast through focus | SPIE Advanced Lithography 2013 | 2013 |
| Yi-Bo Liao, Meng-Hsueh Chiang, Nattapol Damrongplasit, Tsu-Jae King Liu | 6-T SRAM Cell Design with Gate-All-Around Silicon Nanowire MOSFETs | the 20th International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) | 2013 |
| Suchit Bhattarai, Patrick Naulleau, Andy Neureuther | Simulation of the Relationship Between Sensitivity and LWR in an EUV Resist with Photo-Decomposable Quencher | SPIE Advanced Lithography Conference | 2013 |
| John Lee, Puneet Gupta and Fedor Pikus | Parametric Hierarchy Recovery in Layout Extracted Netlists | IEEE Computer Society Annual Symposium on VLSI | 2012 |
| John Lee and Puneet Gupta | Impact of Range and Precision in Technology on Cell-Based Design | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 2012 |
| R. S. Ghaida and P. Gupta | DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2012 |
| Ying Qiao, Kun Qian, Costas J. Spanos | Variability-Aware Compact Model Characterization for Statistical Circuit Design Optimization | IEEE/ACM International Conference on Computer-Aided Design 2012 | 2012 |
| Rani S. Ghaida, Kanak B. Agarwal, Lars W. Liebmann, Sani R. Nasif, Puneet Gupta | A Novel Methodology for Triple/Multiple-Patterning Layout Decomposition | SPIE Advanced Lithography Symposium | 2012 |
| Rani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta | A Methodology for the Early Exploration of Design Rules for Multiple-Patterning Technologies | IEEE/ACM International Conference on Computer-Aided Design 2012 | 2012 |
| Tuck-Boon Chan and Andrew B. Kahng | Tunable Sensors for Process-Aware Voltage Scaling | IEEE/ACM International Conference on Computer-Aided Design 2012 | 2012 |
| N. Xu, C. Shin, F. Andrieu, B. Ho, W. Xiong, B.-Y. Nguyen, M. Choi, O. Weber, V. Moroz, O. Faynot, T. Poiroux and T.-J. King Liu | Effectiveness of Strained-Si Technology for Thin-Body MOSFETs | International SOI Conference (Invited Paper) | 2012 |
| G. Leung, L. Lai, P. Gupta, and C. O. Chui, | Device and Circuit Level Variability Caused by Line Edge Roughness for Sub-32nm Finfet Technologies | IEEE Transactions on Electronic Devices | 2012 |
| Nuo Xu, F. Andrieu, B. Ho, B.-Y. Nguyen, O. Weber, C. Mazure, O. Faynot, T. Poiroux and T.-J. King Liu | Impact of Back Biasing on Carrier Transport in Ultra-Thin-Body and BOX (UTBB) Fully Depleted SOI MOSFETs | 2012 Symposium on VLSI Technology | 2012 |
| Abde Ali Kagalwalla, Swamy Muddu, Luigi Capodieci, Coby Zelnik and Puneet Gupta | Design-of-Experiments Based Design Rule Exploration | SPIE Advanced Lithography | 2012 |
| Abde Ali Kagalwalla, Puneet Gupta, Chris Progler and Steve McDonald | Design-Aware Mask Inspection | IEEE Tran. on Computer-Aided Design of Integrated Circuits and Systems | 2012 |
| T.-B. Chan, P. Gupta, A. B. Kahng and L. Lai | DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators | International Symposium on Quality Electronic Design, March 19, 2012 | 2012 |
| John D. Gerling*, Zhongsheng S. Luo, Vorrada Loryuenyong, and Nathan W. Cheung | A Ubiquitous Optical Microsystem Platform for Lab-on-a-Chip with Application to Optical Metrology and Chemical Sensing | to be Presented at Analytix-2012 Conference, March 23-25, 2012. Beijing, China | 2012 |
| Nuo Xu, Byron Ho, Munkang Choi, Victor Moroz, Tsu-Jae King Liu | Effectiveness of Stressors in Aggressively Scaled FinFETs | submitted to IEEE Transactions on Electron Devices, 2012 | 2012 |
| Nuo Xu, Byron Ho, Francois Andrieu, Lee Smith, Bich-Yen Nguyen, Olivier Weber, Thiery Poroux, Olivier Faynot, Tsu-Jae King Liu | Carrier Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs | IEEE Electron Device Letters, Vol.33, Issue 3, 2012 | 2012 |
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