Vertical GaN MIS-FET for high voltage and high power application, monolithically integrated circuit with Si CMOS

A major hurdle for advancement of EUV lithography is the development of a thorough understanding of resist patterning phenomena. The combination of photon shot noise and a plethora of other stochastic phenomena ultimately limit the end product of even the most well-resolved aerial images. I aim to study one major source of randomness in the EUVL process: the diffusion of photo-generated acid during post exposure bake (PEB) in chemically amplified resists (CAR). To attack this question, experiments were coupled with stochastic modeling in order to glean insight into acid diffusion mechanisms and parameters

Fabrication of Silicon Interconnect Fabrics using Maskless Lithography

Develop methods and framework for system partitioning and re-integration on Si-Interconnect fabric. Upgradable Architecture design for modular systems. Also interested in developing tools and architectures for stochastic computing. On the DFM side, working on methodology and design techniques to mitigate the affects of growing minimum metal area rules.

(1): 3D simulation of high-efficiency EUV etched phase-shift mask. (2): Aberration measurement through off-axis illumination of a weak diffuser