C-DEN Thrusts

Faculty Research Thrusts

Patterning
Integration
Design Enablement

PATTERNING THRUST. (Andrew Neureuther, Patrick Naulleau, Laura Waller, Jane Chang)
Our focus areas in the Patterning Thrust are EUV, phase-based metrology, and plasma etch.

EUV.

We will address basic construction questions: including absorber materials and mask structure (reduced height, etched multilayer, multilayer absorbers, …). In particular we will focus on implications to high NA EUV options including both anamorphic and nonanamorphic designs.
We will study wafer-level sensitivities to mask parameters in terms of mask variation induced CDU. For example, the question of mask height “swing curve” effects will be explored based on current and potential future mask materials and architectures.
We will investigate methods for acceleration of rigorous simulations with off-axis sources for high NA EUV simulations.
We will explore the potential of EUV scatterometry applied to EUV mask CD metrology and potential extension to profile analysis.
We will explore image-based system identification methods, specifically as applied to insitu measurement of wavefront aberrations in mask inspection.
We will explore high speed computation methods to study the CDU impact of fall-on particles on EUV pellicles, enabling arbitrary pupil fill, pattern structure, and pellicle offset to be studied.
We will explore the application of soft-x-ray SAXS/WAXS in the 3D characterization of fine resist patterns and potential application of the method to chemical metrology of latent images.
We will study stochastic limitations in both e-beam and EUV resist including both radiation effects and material effects potentially extending to the development step. This effort will necessarily include building a fundamental understanding of radiation chemistry processes for both e-beam and EUV exposures.
Strengthen the fundamental understanding of non-chemically amplified radiation chemistry processes.
We will explore pattern and process-informed variability requirements and study the correlation of these requirements to the industry standard requirements based on traditional metrics of LWR and contact CDU.
Study post-processing methods for reduction of pattern variability, example methods including etch, alternative develop processes, selective deposition
Improved-accuracy non-stochastic photoresist models, in particular in the realm of dissolution/mechanical properties. Relevant phenomena include the collapse of features during and after development, and resist flow during spin-coating of patterned topographies for planarization.

Phase-based Metrology.

We will develop accurate algorithms and image capture design for very accurate (~1nm) phase retrieval at diffraction-limited lateral resolution with arbitrary sources (partial coherence), captured with either defocus or source coding.
We will use the analysis of mask imaging at DUV and EUV such as on DUV-AIMS, EUVAIMS and SHARP to capture non-ideal mask performance to support advanced DUV and emerging EUV OPC models as well as to monitor variations in mask materials and their pattering uniformity across photomasks.
We will investigate computational imaging methods for characterizing and mitigating EPE in the production line.

Plasma Etch.

Along with lithography advances, plasma processing has been enabling to the extension of large-scale integrated circuit patterning to ever-smaller dimensions. Transport limitations cause variation in the ion and neutral fluxes and ratios within a high aspect ratio feature and across large scale wafers. Thus, leveraging surface reaction kinetics becomes critical to circumvent these variability mechanisms and achieve atomic precision in patterning and selectivity. We will focus on the design and selection of viable etching chemistry for complex metal stacks. Chemical etching of metals is typically difficult in the gas phase due to the difficulty to direct the chemical bond formation. Surface modification of the metals is often needed to allow for or control subsequent etching reactions. This is also a critical step in realizing atomic etching of metals where materials are removed layer by layer from the surface with controllability.

INTEGRATION THRUST.

(Subu Iyer, Shadi Dayeh)

Our focus areas in the Integration Thrust are large-area maskless patterning, contact engineering, vertical-channel device fabrication, and heterogeneous integration of III-V devices on silicon.

Maskless Patterning.

Cost-effective maskless patterning of metal lines and dielectrics on large-area substrates could be critical to future multi-chip integration methods. While conventional 248nm lithography can expose micron-size features, these tend to be either scanner -based or step-and-repeat. In addition, these methods require a mask. For future applications, we would like to expose areas comparable to a full 200 mm diameter wafer with a throughput of 5x compared to today's step-and-repeat methods, but without the use of masks. We would like to develop a system that allows for use of direct write optical lithography or additive high resolution high throughput printing of 2-10 micrometer features.

Contact Engineering.

Contact engineering is increasingly becoming one of the most challenging aspects of devices. We will utilize timed thermal oxidation for the selective atomic layer etching of Si and InGaAs to 2nm thick and 5 nm long channels. Their specific contact resistance (with alloy/compound contacts of Ni and respective Si and InGaAs dopants) will be extracted, and their contacts’ interface morphology and strain will be characterized by high resolution transmission electron microscopy.

Vertical Channel Devices.

Complementing design-level assessments of vertical channel devices, we will investigate fabrication methods for the same. The realization of vertical nanowire transistors requires innovations on preparation (seeded growth is not thermodynamically possible, and etching with smooth surfaces is not physically attainable), and consequent fabrication steps. We will engineer template (and sacrificial) structures to selectively grow thin nanowires on their facets, and fabricate vertical channel transistors on the thin membranes.

Heterogeneous Integration.

Heterogeneous integration of III-V devices on silicon is a potential path to improved device performance. The growth temperature for GaN is suitable for the evaporation of native Si oxides, and for the reflow of Si atoms to form smooth Si nanowires. Heteroepitaxy of GaN on such Si nanowires when followed by a temperature increase to evaporate the Si nanowires will enable us to grow very thin body GaN transistor channels on Si. We will investigate the thermal expansion and crystallographic orientations for which dilation without cracking of GaN on Si is possible (we validated the <11-20> to be a suitable direction in a separate large area growth study).

DESIGN ENABLEMENT THRUST. (Puneet Gupta, Andrew Kahng)
Our focus areas in the Design Enablement Thrust are pathfinding frameworks (for DSA and for 3D integration), design use of novel integration primitives, and a modeling and optimization chain to determine “Ultimate Nx” – the limits of the PPAC envelope for a given node definition.

Pathfinding.

Continuing our design-aware technology exploration efforts from IMPACT+, we will develop pathfinding frameworks especially for Directed Self Assembly (DSA) and 3D integration.
DSA has its own set of pathfinding challenges with choice of complementary lithography, block co-polymer and defectivity tradeoffs. We will develop an optimal and flexible framework to explore viability of different hybrid DSA lithography schemes for a suite of benchmark design layouts.
By the N5 time frame, heterogeneous 2.5D/3D integration will contribute significantly to value and cost scaling in key product classes. To comprehend PPAC impacts of technology options (e.g., microbump pitch, BEOL stack, on-chip regulation, new interconnect material, new fanout technology, etc.) and mitigate risk, we will develop a pathfinding tool for 3D. Questions that will be answerable by this tool include “what is the sensitivity of achievable PPAC to a given technology option”, “what X% technology improvement will improve the {P,P,A,C} dimension by Y%” (e.g., reduction of Vt variability, reduction of vertical interconnect pitch, enablement of 5T cell architecture), or “how should a given monodie SoC best split into an SiP”.

Ultimate Nx.

A related task is to project what is achievable. We will develop an “Ultimate Nx” (e.g., N7, N5, N4) technology evaluation framework for N7 and below nodes. Key elements are (1) projection of key design blocks spanning key standard cells, critical paths and MCU/CPU/DSP IPs, and (2) “Ultimate Nx” optimization codes. We think of (2) as “DTCO with a solid foundation of core optimizations”: it spans EDA-type optimizations (sizing, P&R (such as mixed-height placement optimization from UCSD) and design closure), library synthesis (UCLA DRE), scalable ILP-based solvers (detailed place, route, cut mask, etc. from UCSD), and mask strategy / BEOL stack vs. PPAC optimizations (mix of 1x, 2x, 4x uni-/bi-directional layers; line-space duty cycle tweaks, etc.). Inputs to “Ultimate X” can include manufacturing cost and design rule assumptions, along with PPAC objectives and constraints. Outputs are technology choices and supporting implementation flow prototypes to confirm claimed PPAC benefits.

Novel Integration Primitives.

In addition to 3D, other novel within-chip integration primitives are likely to be key to density and performance scaling in an era where complexities restrictive patterning schemes will limit layout density improvement. Examples include vertical channel devices, buried interconnect and double height “super vias”. We will evaluate these by developing associated layout generators and physical implementation flows.